Monday, January 17, 2011

Intigrting handelc code into VHDL design (VHDL as TOP level)



1. Create new project in DK suite
File -> new -> project
Give the project name as xor_gate

2. add handelc source file to adder
            File -. New -> file -> handelc source file
            Give name as xor_gate

3. Add the following code

set clock = external "p77";
set reset = external with {active_low=0};
 

void main()
{
    unsigned 1 in1,in2;
    unsigned 1 result;
while(1)
    {
interface port_in(unsigned 1 IN1) InBus();
interface port_in(unsigned 1 IN2) InBus1();
interface port_out() OutBus(unsigned 1 OutPort = result);
   
    in1=InBus.IN1;
    in2=InBus1.IN2;
       
    result=in1 ^ in2;
     
    }
  }

4. set active configuration to vhdl

5. Build the project.  To build press f7


6. Create  an ISE project having name adder
Fine -> new project -> give name as adder
Press next

Select the device and language as VHDL

Press next and finidh
7. Add new source to project
 Right click to project and select new source

Select VHDL package and give name as agility

Click next finish
8. open the installed folder for DK design suity (C:\Program Files\Agility\DK\vhdl) open agility file copy the content of file and replace the conteng of new created agility package with this content.
.

9. Again select new source and select VHDL library and give name to librarty as agility

Click next anf finish
Goto library tab select the agility package available in work library. Right click to package and select move to library

Then select agility as library

10. Add new source as a vhdl module having name as adder to design

Click next-> next -> finish

Replace the code of adder with following code

----------------------------------------------------------------------------------
-- Design Name: Half Adder Using HandelC Cores
-- Company: Shivaji University
-- Engineer: Dr S A Shinde
-- Module Name:    top_module - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_module is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
                                      sum : out  STD_LOGIC;
                                      carry : out  STD_LOGIC;
                                      reset : in  STD_LOGIC;
                                      clk: in  STD_LOGIC);
end top_module;

architecture Behavioral of top_module is
component xor_gate  PORT (
    IN1 : IN std_logic;
    IN2 : IN std_logic;
    OutPort : OUT std_logic;
    PADIN_xor_gate_hcc_ResetInPin : IN std_logic;
    PIN_p77 : IN std_logic);
END COMPONENT;

component and_gate  PORT (
    IN1 : IN std_logic;
    IN2 : IN std_logic;
    OutPort : OUT std_logic;
    PADIN_and_gate_hcc_ResetInPin : IN std_logic;
    PIN_p77 : IN std_logic);
END COMPONENT;
                                     
begin
U1 : xor_gate port map(a,b,sum,reset,clk);
U2 : and_gate port map(a,b,carry,reset,clk);
end Behavioral;


Then add the xor_gate component from handelc to vhdl code

11. similary creat a project of name and_gate having handelc source fime as and_gate.hcc
and_gate hcc

set clock = external "p77";
set reset = external with {active_low=0};
 

void main()
{
    unsigned 1 in1,in2;
    unsigned 1 result;
while(1)
    {
interface port_in(unsigned 1 IN1) InBus();
interface port_in(unsigned 1 IN2) InBus1();
interface port_out() OutBus(unsigned 1 OutPort = result);
   
    in1=InBus.IN1;
    in2=InBus1.IN2;
       
    result=in1 & in2;
     
    }
 }
12. build for VHDL and add the generated vhdl file to xilinx ISE project


Then synthesis the design


Then the two components are xor_gate and and_gate are connected to form adder. The two components are generated using handelc and incorporated as a component in VHDL as top level design.


Monday, December 20, 2010

Dr. Santosh Shinde

Assistant Professor,
Department of Electronics,
Shivaji University,
Kolhapur - 416 004.
email - sas.vlsi[at]gmail.com



Education_______________________________

v  Ph. D. (VLSI Design) (2009) Specialized in Network on Chip Design, Title of the thesis: “Development of Reconfigurable FPGA based Systemc for Circumventing SPAM Email”

v  Masters in Electronics, M.Sc. (2006) Specialized in Communication Electronics and Computer Networking, . Title of Dissertation: “Device Control through SMS”.


v  Bachelor in Electronics,  B.Sc. (2004),  Secured Distinction .

Awards, Honors and Fellowships_____________________________

  •   Research Fellowship awarded by University Grants Commission (UGC) India  under the grant scheme for supporting meritorious Ph.D. work.
  •  Aklavya Scholarship (Dedicated for the Outstanding Students) for securing highest marks at Graduation

Technical Skills___________________________________

  • Expertise in VHDL Verilog  HandelC and SystemC programming.
  •  Experience in FPGA based System on Chip and Network on Chip Design.
  •  Well Familiar with ASIC design flow, verification and validation and timing analysis, place and route and design for test.
  •  Sound knowledge in Embedded C, ANSI C, and C++, Matlab programming.
  •  Experience in Digital and Analog circuit design, Verification, Embedded System Programming, software development (C, C++, Assembly language, Embedded C and) in the field of information technology, Networking, Communication, Security, consumer electronics and research and development.
  • Experience in developing test system and test suites for testing electronic systems.
  •  Experience in Assembly programming - 8086, 8085, 8051 and PIC.
  •  Well familiarity with  interfacing such as ADC, DAC, sensors and test equipments like oscilloscope, function generator, etc.
  •  Good understanding of the communication protocols such as CAN, I2C, RS-232, RS-485.
  •  Practice in working with the diverse Engineering Packages like Synopsis Design Compiler, Mentor Graphics – Modelsim,  MATLAB, Simulink, HSPICE, ORCAD-PSPICE, KEIL, Xilinx Webpack, Xilinx Embedded design Kit (EDK) , DK design suit for HandelC.
  •  Good practice in building microprocessor/microcontroller based applications including circuit design as well as programming using assembly language and Embedded C.
  •  Good understanding of the error control coding schemes such as Convolution encoding, and RS encoding Viterbi decoder.
  •  Good understanding computer systems architecture and systems programming, Data structures and algorithms.
  •  Experience on encryption algorithms such as RC4, AES-128 bit, DES, RC5, etc.
  •  Experience on Design System on Chip (SoC) application for networking such as web server, POP client, SMTP server.
  •  Good Understanding of embedded TCP/IP stack and working with LWIP stack.
  •  Well Familiar with Designing Soft IP cores and their reuse in FPGA.
  •  Working with Different soft microprocessor cores like MicroBlaze, PicoBlaze and PowerPC.
  •  Xilinx FPGA used: - Spartan family XC3s400, XC3s200, XC3S500E. (Xilinx Spartan 3E Starter Kit).
  •  Operating Systems: - Windows 98, Windows NT, Windows XP, Windows Vista, Linux (Redhat ,openSUSE and Ubuntu), Unix.