1. Create new project in DK suite
File -> new -> project
Give the project name as xor_gate
2. add handelc source file to adder
File -. New -> file -> handelc source file
Give name as xor_gate
3. Add the following code
set clock = external "p77";
set reset = external with {active_low=0};
void main()
{
unsigned 1 in1,in2;
unsigned 1 result;
while(1)
{
interface port_in(unsigned 1 IN1) InBus();
interface port_in(unsigned 1 IN2) InBus1();
interface port_out() OutBus(unsigned 1 OutPort = result);
in1=InBus.IN1;
in2=InBus1.IN2;
result=in1 ^ in2;
}
}
4. set active configuration to vhdl
5. Build the project. To build press f7
6. Create an ISE project having name adder
Fine -> new project -> give name as adder
Press next
Select the device and language as VHDL
Press next and finidh
7. Add new source to project
Right click to project and select new source
Select VHDL package and give name as agility
Click next finish
8. open the installed folder for DK design suity (C:\Program Files\Agility\DK\vhdl) open agility file copy the content of file and replace the conteng of new created agility package with this content.
.
9. Again select new source and select VHDL library and give name to librarty as agility
Click next anf finish
Goto library tab select the agility package available in work library. Right click to package and select move to library 
Then select agility as library
10. Add new source as a vhdl module having name as adder to design
Click next-> next -> finish
Replace the code of adder with following code
----------------------------------------------------------------------------------
-- Design Name: Half Adder Using HandelC Cores
-- Company: Shivaji University
-- Engineer: Dr S A Shinde
-- Module Name: top_module - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_module is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC;
reset : in STD_LOGIC;
clk: in STD_LOGIC);
end top_module;
architecture Behavioral of top_module is
component xor_gate PORT (
IN1 : IN std_logic;
IN2 : IN std_logic;
OutPort : OUT std_logic;
PADIN_xor_gate_hcc_ResetInPin : IN std_logic;
PIN_p77 : IN std_logic);
END COMPONENT;
component and_gate PORT (
IN1 : IN std_logic;
IN2 : IN std_logic;
OutPort : OUT std_logic;
PADIN_and_gate_hcc_ResetInPin : IN std_logic;
PIN_p77 : IN std_logic);
END COMPONENT;
begin
U1 : xor_gate port map(a,b,sum,reset,clk);
U2 : and_gate port map(a,b,carry,reset,clk);
end Behavioral;
Then add the xor_gate component from handelc to vhdl code
11. similary creat a project of name and_gate having handelc source fime as and_gate.hcc
and_gate hcc
set clock = external "p77";
set reset = external with {active_low=0};
void main()
{
unsigned 1 in1,in2;
unsigned 1 result;
while(1)
{
interface port_in(unsigned 1 IN1) InBus();
interface port_in(unsigned 1 IN2) InBus1();
interface port_out() OutBus(unsigned 1 OutPort = result);
in1=InBus.IN1;
in2=InBus1.IN2;
result=in1 & in2;
}
}
12. build for VHDL and add the generated vhdl file to xilinx ISE project
Then synthesis the design
Then the two components are xor_gate and and_gate are connected to form adder. The two components are generated using handelc and incorporated as a component in VHDL as top level design.
